1. Field of Invention
The present invention relates to a method of manufacturing an integrated circuit. More particularly, the present invention relates to an etching method for making openings of different depths.
2. Description of Related Art
In the integrated circuit device, devices are often electrically connected via the formation of contacts. However, since the heights of the connected devices are not the same, the depths of the contacts are different. In case that a dynamic random access memory (DRAM), the substrate on which the DRAM is formed, the gate of a field effect transistor on the substrate, and a bit line all have different surface level, contacts connecting these regions are formed in the dielectric layer with different depths.
In the conventional method for forming contact openings of different depths in a dielectric layer, a mixture of fluoride-based methane group and Oxygen (O.sub.2), Carbon Monoxide (CO) and Argon (Ar) is used as the etching formula to etch a silicon oxide dielectric layer. The etching process is performed in a magnetic enhanced reactive ion etching oxide etcher (MERIEOE). As the integration of a semiconductor increases, the aspect ratio of the contact gradually increases, so that such etching faces the problem of a poor etching selectivity, and an intractable contact profile.
In FIG. 1A, using DRAM as an example, the problems faced by etching contact openings of different depths in the prior art are illustrated and describe hereinafter. Referring to FIG. 1A, a substrate 100, a polysilicon layer over the substrate 100 or a gate 104, and a polysilicon layer 110 formed as a bit line have different surface levels in the figure. The silicon oxide dielectric layer 112 and the cape layer are etched to form openings 118, 114, and 116 to expose a source/drain region 106, a gate 104 and a polysilicon layer 110, respectively. By the above etching process, the etching process cannot be terminated at the surface of the substrate 100 or the gate 104 because the etching gas often has an insufficient selective ratio for the dielectric layer 112 and the substrate 100, or the dielectric layer 112 and the gate 104. Thus, the polysilicon layer 110, the substrate 100 or the gate 104 is damaged as shown by the dotted lines in FIG. 1A.
When the integration level further increases, the thickness of the dielectric layer 112 becomes thicker. The size of contact openings also diminishes. This obviously increases aspect ratio of the contact openings and greatly increases the etching difficulty. For example, when the thickness of the dielectric layer 112 is greater than 2.2 .mu.m, and the size of the contact openings 114 and 116 is smaller than 0.4 82 m, the contact openings 114 and 116 having a high aspect ratio to cause an intractable profile for above etching process. FIG. 1B illustrates the etching step of contact openings 114 and 116 having high aspect ratios. The openings 116 and 118 having a larger depth are formed with a bowing profile. A problem with respect to the resistivity and reliability of the device is resulted by poor filling effect of the contact openings 114 and 116 with a metal layer.